Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable general interconnect structure.
The interconnect structure and logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Some FPGAs include blocks of dedicated logic in the CLB array. “Dedicated logic” is hard-coded logic designed to perform a specific function, although the dedicated logic can be programmable to modify the function. For example, the Xilinx Virtex®-II FPGA includes blocks of Random Access Memory (BRAM), as shown in FIG. 1. The Xilinx Virtex-II FPGA is described in detail in pages 33–75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.
As shown in FIG. 1, in the Virtex-II FPGA the array of logic blocks and programmable general interconnect is designed as an array of “tiles”. The tile approach both facilitates the physical implementation of the programmable interconnect structure and makes feasible the routing software that implements a user design in the FPGA. One tile can include, for example, a CLB 104, which includes a block of logic (configurable logic element or CLE 101a). Each CLB includes an interconnect area 105 in addition to the CLE 101, and in fact interconnect area 105 typically consumes a much larger percentage of the available area than CLE 101.
As is well known in the art, interconnect area 105 includes a hierarchy of interconnect lines and several switch matrices for programmably coupling the interconnect lines to each other and to input and output ports of the CLE. Thus, interconnect area 105 constitutes a portion of the programmable general interconnect structure of the FPGA.
In the Virtex-II FPGA, each BRAM block 106 consumes more than one tile in the CLB array, as shown in FIG. 1. The RAM logic 103 is surrounded by programmable interconnect 107, e.g., similar to interconnect 105 in CLB 104. As in CLB 104, the interconnect area of the BRAM block consumes a significant amount of the surface area available for the block.
The tiles devoted to implementing specialized functions are often arranged in columns, as shown in FIG. 1, to simplify the routing of user designs. Another advantage of placing the specialized blocks in separate columns is that the specialized tiles can be of a different width from the CLB tiles. When a columnar arrangement is used, the height of each specialized block is the same as, or a multiple of, the height of one CLB tile.
In the Virtex-II FPGA, more than one column of CLBs typically separates each column of BRAM blocks, as shown on page 60 of the Virtex-II Platform FPGA Handbook, referenced above. In FIG. 1, only one column of CLBs is shown between each column of BRAM blocks, to clarify the figure.
More advanced FPGAs can include more complicated logic blocks in the CLB array. For example, the Xilinx Virtex-II Pro™ FPGA includes embedded processor blocks in addition to the blocks available in the Virtex-II FPGA. The Xilinx Virtex-II Pro FPGA is described in detail in pages 19–71 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., which pages are incorporated herein by reference.
FIG. 2 shows how the processor blocks are embedded in the Virtex-II Pro CLB array. In essence, the BRAM blocks illustrated in FIG. 1 are spread apart vertically to provide room for additional tile rows that include the processor blocks. (In the Virtex-II Pro CLB arrays, a processor block typically covers many more tiles than are shown in FIG. 2, both vertically and horizontally. The number of tiles has been reduced in the figure, for clarity.) Each processor block includes a processor (uP 211), two on-chip memory control blocks (OCMs 212a, 212b), and programmable interconnect 213. The processor and the OCMs are tightly coupled together, i.e., they are interconnected by a dedicated interface rather than being coupled together using the programmable interconnect structure of the FPGA. Additionally, the OCMs provide dedicated interfaces between the processor 211 and the adjacent BRAM blocks 103a–103d. 
The OCMs serve two main purposes. Firstly, and most obviously, the OCMs function to adapt the defined interface required by the processor 211 to the needs of the BRAM blocks. For example, the OCMs perform address decoding functions. Additionally, however, the interface between the processor 211 and RAM logic 103 might not be able to function at the same maximum frequency as the processor itself. By operating the OCM blocks at a slower clock frequency than the processor, the processor is freed from having to accommodate this external frequency limitation.
However, there are many applications where it is desirable to operate an electronic system at the highest possible clock frequency. Many of these systems can also benefit from the advantages of reprogrammability. Therefore, it is desirable to provide programmable logic devices (PLDs) incorporating processor functionality wherein the memory access speed of the embedded processors is not limited by timing delays built into memory control blocks.
Further, there are many applications that can benefit from the availability of processor functionality in a PLD, but do not require the computing power provided, for example, by the powerful processors included in the Virtex-II Pro FPGA. Many PLD users would benefit from the addition of processor capability, but prefer a lower cost to a larger die size (and the consequent increase in price) including processor capability. Further, some PLD users do not need and would not use the processor capability. It is desirable to provide a PLD that can meet the needs of each of these users. Therefore, it is desirable to provide processor capability in a PLD while minimizing the increase in die size caused by the modification.
It is further desirable to minimize the disruption to the fabric of the PLD. When the processor is not used, it is desirable to have the capability of making the presence of the processor transparent to the user. Further, it is desirable to minimize the effect on the PLD routing software of modifying the PLD to include processor capability.